Rhyscitlema system disyware

The Rhyscitlema computer application shall mainly be available as a system disyware. This was originally started as the prototype deliverable of a final year project, and is expected to reach a release ready for the end-user by December 2018. It is written entirely in the Verilog HDL (Hardware Description Language). That is all the algorithms constituting the computer disyware application are written as hardware descriptions in scratch Verilog HDL. Here the hardware abstraction and the kernel source code are provided.

...to be updated...

Download the available bitstream - only for the Digilent Nexys-3 Spartan-6 FPGA development board.

The image below shows the interior of the top-level module of the Rhyscitlema computer application as a digital system logic. The top-level input and output ports directly connect to external devices such as the keyboard, mouse, screen and memory. Therefore they completely depend on the particular development board used. They directly connect to the Kernel module, which implements the drivers or controllers for the external hardware, thereby serving as interface between the actual platform-independent application and the underlying hardware. This actual application is a module named Disyware and is highlighted on the image. It connects only to the kernel and is therefore independent of the development board used.

The Rhyscitlema Disyware Logic

The image below shows the current output as seen on the screen (VGA 800x600x60Hz). The display is the graphical user interface. The application is still under development.

The Rhyscitlema Disyware GUI